Defines the PLCP error generation controls permitted at this interface. This object is bit-mapped and can permit a maximum of 8 simultaneous error controls. Once the controls are initiated, the selected errors are generated for a period of time specified by object 'atmPhyConfPlcpControlTimer'. Error generation can be restarted at any time. To enable a specific control, its bit must be set. To disable a specific control, its bit must be reset. The controls are assigned the following bits: (bit-0): Controls the generation of a PLCP yellow alarm signal by setting the yellow signal bit position in the path status octet (G1) within consecutive PLCP frames. (bit-1): Controls the generation of a PLCP Far End Block Errors (FEBE) by inserting a single far end block error within consecutive PLCP frames. (bit-2): Controls the generation of PLCP Bit Interleave Parity (BIP) errors by inserting a single bit interleave parity error within consecutive PLCP frames. (bit-3): Controls the generation of frame alignment pattern errors by inserting a single bit error in each A1 & A2 octets within consecutive PLCP frames. (bit-4): Controls the generation of parity errors by inserting a parity error into each path overhead identification (POHID) octet within consecutive PLCP frames.